Leadframeless package structure and method

ABSTRACT

A method for providing a leadframeless package structure is provided. The method includes providing a temporary carrier. The temporary carrier is coupled to a metal foil layer with a temporary adhesive layer. An integrated circuit chip is coupled to the metal foil layer. The temporary adhesive layer and the temporary carrier are removed to form the leadframeless package structure after molding.

TECHNICAL FIELD OF THE INVENTION

[0001] The present invention is directed in general to integratedcircuits and, more specifically, to a leadframeless package structureand method.

BACKGROUND OF THE INVENTION

[0002] A conventional integrated circuit package generally comprises aleadframe made from 0.005-inch thick metal, an integrated circuit madeof silicon, and a protective material to protect the electricalconnections between the integrated circuit and the leadframe. Theleadframe acts as an electrical and mechanical interface between theintegrated circuit and the printed circuit board (PCB) on which theintegrated circuit package is soldered. These packages are generallyknown as Dual-In-Line Package (DIP), Small Outline package (SO), or QuadFlat Package (QFP). In the manufacturing of these packages withleadframes, heavy industrial tools such as stamping and forming arerequired. These tools are expansive and dedicated to one package sizeand pin count. A leadframeless package is highly desirable because itrequires a minimum of dedicated tooling such as, for example, onephotomask and one solder ball fixture.

[0003] Recent development of higher pin count packages has substitutedthe leadframe with a fiberglass material. These packages are generallyknown as Ball Grid Array (BGA). The fiberglass material has metal foils(0.0015-inch thick) on the top and bottom sides and conductor patternsare etched on both sides to connect the die to the PCB.

[0004] Conventional packaging options for high performance integratedcircuit dice include the use of a substrate or leadframe as a carrier.These are normally incorporated permanently in the final packagestructure. Disadvantages associated with these package structuresinclude a limited ability to re-use the leadframe or substrate foranother die. The leadframe or substrate becomes a fixed material costfor every package manufactured. The tooling for stamping the leadframeand the artwork for etching new substrates are quite substantial whenthere is a change in die size as the feature size of the integratedcircuit is shrunk. In addition, the substrate or leadframe contributesto the thickness of the package structure, which is generally desired tobe minimized. Also, when solder balls are used with the integratedcircuit die, as in BGA packages, the width and depth of the packagestructure may be greater than desired due to the inclusion of theconnections to the solder balls that are exterior to the areaencompassed by the die.

SUMMARY OF THE INVENTION

[0005] In accordance with the present invention, a leadframeless packagestructure and method are provided that substantially eliminate or reducedisadvantages and problems associated with conventional systems andmethods. In particular, a temporary carrier that is coupled to thestructure during formation is removed after formation is complete,resulting in a structure without a leadframe.

[0006] According to one embodiment of the present invention, aleadframeless package structure is provided that includes a temporarycarrier, a metal foil layer, an integrated circuit chip, a plurality ofbonding wires, and a molding compound. After attaching the metal foillayer to the temporary adhesive/carrier system, the metal foil ispatterned and etched (using conventional techniques commonly known inthe PCB industry) to produce a set of planar electrical traces, dieattach pads and bonding pads. The die is then attached (usingconventional semiconductor assembly techniques) to the special dieattach pad formed in the metal foil. Subsequently, conventional wirebondtechniques are used to form electrical interconnects between the die andthe electrical traces in the metal foil. Special pads are also providedin the metal foil for this purpose. Following a molding step, whichencases the delicate wirebonds and die with a plastic which providesrigidity and protection, the temporary carrier portion is removed.

[0007] Technical advantages of one or more embodiments of the presentinvention include providing an improved leadframeless package structure.In a particular embodiment, a temporary carrier is coupled to thestructure with a suitable adhesive layer during formation. The adhesiveand carrier system are removed after molding. As a result, the chipsattached to the structure have no leadframes or substrates. Accordingly,the leadframeless package structure has a reduced fixed cost ofmaterials, is capable of accommodating large and small dice at minimumtooling cost, has a reduced thickness due to the absence of a carrier,and can provide a chip-scale package when second level interconnects(e.g., solder pads) are located within the approximate footprint of thedie.

[0008] Other technical advantages will be readily apparent to oneskilled in the art from the following figures, description, and claims.

[0009] Before undertaking the DETAILED DESCRIPTION OF THE INVENTION, itmay be advantageous to set forth definitions of certain words andphrases used throughout this patent document: the terms “include” and“comprise,” as well as derivatives thereof, mean inclusion withoutlimitation; the term “or,” is inclusive, meaning and/or; the phrases“associated with” and “associated therewith,” as well as derivativesthereof, may mean to include, be included within, interconnect with,contain, be contained within, connect to or with, couple to or with, becommunicable with, cooperate with, interleave, juxtapose, be proximateto, be bound to or with, have, have a property of, or the like; and theterm “controller” means any device, system or part thereof that controlsat least one operation, such a device may be implemented in hardware,firmware or software, or some combination of at least two of the same.It should be noted that the functionality associated with any particularcontroller may be centralized or distributed, whether locally orremotely. Definitions for certain words and phrases are providedthroughout this patent document, those of ordinary skill in the artshould understand that in many, if not most instances, such definitionsapply to prior, as well as future uses of such defined words andphrases.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present invention andits advantages, reference is now made to the following description takenin conjunction with the accompanying drawings, wherein like referencenumerals represent like parts, in which:

[0011] FIGS. 1A-E are a series of schematic cross-sectional diagramsillustrating a method for forming a leadframeless package structure inaccordance with one embodiment of the present invention;

[0012] FIGS. 2A-B are schematic cross-sectional diagrams illustrating analternate embodiment for the steps illustrated in FIGS. 1D-E; and

[0013]FIG. 3A is a schematic top-view diagram illustrating circuitpatterns formed in the metal foil layer of FIG. 1 or 2 in accordancewith one embodiment of the present invention;

[0014]FIG. 3B is a schematic top-view diagram illustrating circuitpatterns formed in the metal foil layer of FIG. 1 or 2 in accordancewith another embodiment of the present invention; and

[0015] FIGS. 4A-D are schematic top-view diagrams illustrating theleadframeless package structure of FIG. 1 or 2 in accordance withmultiple embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0016]FIGS. 1 through 4, discussed below, and the various embodimentsused to describe the principles of the present invention in this patentdocument are by way of illustration only and should not be construed inany way to limit the scope of the invention. Those skilled in the artwill understand that the principles of the present invention may beimplemented for any suitably arranged leadframeless package structure.

[0017] Referring to FIG. 1A, an initial structure 10 for a leadframelesspackage structure comprises a temporary carrier 20 and a temporaryadhesive layer 30. The temporary carrier 20 may comprise any rigid orsemi-rigid material that is compatible with the chemical and thermalprocesses encountered in the normal semiconductor packaging assemblyprocess which will serve as a base on which the leadframeless packagestructure may be formed. Examples of such materials would includeconventional metals, such as stainless steel or aluminum, and hightemperature plastics and plastic composites, such as laminate epoxyfiberglass.

[0018] The temporary adhesive layer 30 is formed over the temporarycarrier 20. The temporary adhesive layer 30 may be formed by anysuitable means. The temporary adhesive layer 30 comprises a materialthat may be removed from a metal layer without damage to the metallayer. For example, the temporary adhesive layer 30 may comprisesilicone or other suitable adhesive material.

[0019] Referring to FIG. 1B, a metal foil layer 40 is conventionallyjoined to the temporary adhesive layer 30. According to one embodiment,the metal foil layer 40 comprises gold-plated copper. According toanother embodiment, the metal foil layer 40 comprises copper withoutgold-plating. For this embodiment, after the metal foil layer 40 ispatterned as described in more detail below, a solder mask may be formedoutwardly of the metal foil layer 40 and used to expose solder areas,which may then have gold or other suitable material applied to them.However, it will be understood that the metal foil layer 40 may compriseany suitable conducting material without departing from the scope of thepresent invention. The metal foil layer 40 may be about 5 μm (0.0002inch) thick.

[0020] A mask (not illustrated in FIG. 1B) is conventionally formedoutwardly of the metal foil layer 40. The mask, which comprises amaterial that is sensitive to light, is patterned through a process thatgenerally includes photolithography and etching. The mask forms apattern that corresponds to circuit patterns to be formed in the metalfoil layer 40, with the material of the mask remaining over the metalfoil layer 40 over portions corresponding to the circuit patterns. Theportion of the metal foil layer 40 that is exposed is removed by an etchprocess while the remaining portion of the metal foil layer 40 isprotected by the mask. The temporary adhesive layer 30 is selected to beunaffected or minimally influenced by a brief exposure to etchant. Themask may then be removed with a resist stripping process, resulting inthe circuit patterns being formed in the metal foil layer 40. Top viewsof the structure 10 following this step are illustrated in FIGS. 3A-B.

[0021] Referring to FIG. 1C, a plurality of integrated circuit dies, orchips, 50 are conventionally attached to the metal foil layer 40 with apermanent adhesive 60 either as matrixed groups of related dice or asindividual dice arrayed in a matrix format. The chips 50 may eachcomprise a microprocessor, a microcontroller, a memory device, anapplication-specific integrated circuit, or any other suitable device.As used herein, “each” means every one of at least a subset of theidentified items.

[0022] The permanent adhesive 60 comprises a non-conductive materialthat will adhere to the metal foil layer 40 and to the chips 50indefinitely. For example, the permanent adhesive 60 may comprise anepoxy, such as QMI 536, manufactured by Quantum Materials, Inc., orother suitable adhesive material.

[0023] Referring to FIG. 1D, bonding wires 70 are conventionally formedfrom the chips 50 to the metal foil layer 40. The bonding wires 70 maycomprise a gold alloy or other suitable electrically conductivematerial. The bonding wires 70 serve to couple bond pads on the chips 50to specified metal traces in the circuit patterns in the metal foillayer 40. Solder pads patterned in the specified metal traces may thenbe used to couple the specified areas of the chips 50 to a matingprinted circuit board through solder balls or other suitable couplingmeans, as described below in connection with FIG. 1E.

[0024] A molding compound 80 is conventionally formed outwardly of themetal foil layer 40 and the chips 50. The molding compound 80 forms arigid encasement that covers the metal foil layer 40, the chips 50, andthe bonding wires 70, thereby protecting the electrical connectionsbetween the chips 50 and the metal foil layer 40. The molding compound80 may comprise any suitable insulative material, such as epoxy novolacthermoset plastic_EME 6600, manufactured by Sumitomo Bakelite Co., Ltd.,or the like. The chips 50 may be arrayed in a matrix of groups ofrelated dice or in a matrix array of individual dice. It is possible toovermold the entire array of dice or array of groups of dice at onceusing a single cavity or alternatively to overmold individual dice orindividual groups of dice using a cavity for each group or unit. If theformer method is used, the individual components will need to besingulated from the bulk group using conventional semiconductor assemblymanufacturing techniques.

[0025] Referring to FIG. 1E, the temporary adhesive layer 30 is removedfrom the structure 10, resulting in the removal of the temporary carrier20 as well. The temporary adhesive layer 30 may be removed by thermallysoftening the adhesive bond to the metal foil layer 40 and moldingcompound or by using any other suitable means. The adhesive material ofthe temporary adhesive layer 30 can be selected so that the its adhesionto the temporary carrier 20 is greater than to the metal foil layer 40or the molding compound 80 in a system analogous to liners used totemporarily transport labels or stickers.

[0026] The resulting structure 10 may then be coupled to a printedcircuit board (not illustrated in FIG. 1E) using solder balls or othersuitable coupling means. According to one embodiment, solder balls maybe attached to the structure 10 through the metal foil layer 40 oppositeof and directly underneath each chip 50 in a convention known as “fanin,” as illustrated in FIG. 3A. In this configuration, the solder ballsare placed over the circular portion of the metal traces, and outside ofthe die area, as represented by the dashed-lines in the figure.According to another embodiment, solder balls may be attached to thestructure 10 through the metal foil layer 40 opposite of each chip 50,but underneath an area surrounding the perimeter of the chip 50 in aconvention know as “fan out,” as illustrated in FIG. 3B. It will beunderstood, however, that the coupling means used may be provided in anysuitable manner without departing from the scope of the presentinvention.

[0027] Thus, the structure 10 provides a set of chips 50 withoutleadframes or carriers. Thus, this leadframeless package structure 10has a minimum material cost, is capable of more easily accommodating diesize changes with minimum tooling cost for the patterning of one layerinstead of multiple layers in a BGA substrate, has a reduced thicknessdue to the lack of leadframes or substrates, and provides a chip-scalepackage when the solder pads are arrayed approximately underneath thechip 50.

[0028] FIGS. 2A-B are schematic cross-sectional diagrams illustrating analternate embodiment for the steps illustrated in FIGS. 1D-E. Thus,referring to FIG. 2A, an alternate embodiment is illustrated for thesteps of FIG. 1D.

[0029] As described in connection with FIG. 1D, bonding wires 70 areconventionally formed from the chips 50 to the metal foil layer 40 and amolding compound 80 is conventionally formed outwardly of the metal foillayer 40 and the chips 50. However, for the embodiment illustrated inFIG. 2A, the molding compound 80 is absent from selected areas over thechips 50 such that a surface 90 of each chip 50 is exposed. For thisembodiment, the molding compound 80 may be formed selectively over andaround portions of each chip 50 in order to expose the surface 90 ofeach chip 50.

[0030] Thus, the molding compound 80 is operable to cover the metal foillayer 40, the areas of the chip 50 other than the exposed surface 90,and the bonding wires 70, thereby protecting the electrical connectionsbetween the chips 50 and the metal foil layer 40.

[0031] Referring to FIG. 2B, the temporary adhesive layer 30 is removedfrom the structure 10 as described above in connection with FIG. 1E,resulting in the removal of the temporary carrier 20 as well. Theresulting structure 10 then comprises the exposed surfaces 90 of thechips 50.

[0032] FIGS. 4A-D are schematic top-view diagrams illustrating theleadframeless package structure 10 in accordance with multipleembodiments of the present invention. For each of the embodimentsillustrated in FIGS. 4A-D, the chips 50 may comprise the chips 50illustrated in FIGS. 1 and 2 and may be formed in a leadframelesspackage structure 10, as described above in connection with FIGS. 1 and2.

[0033] For the embodiment illustrated in FIG. 4A, a discrete cavity isused to form a molded section 120 for each chip 50, while for theembodiment illustrated in FIG. 4B, a discrete cavity is used to form amolded section 130 for each of a plurality of a matrices of chips 50.Each matrix of chips 50 shares a single substrate and forms a multi-chipmodule. Although the illustrated embodiment comprises four chips 50 inthe multi-chip module, it will be understood that each multi-chip modulemay comprise any suitable number of chips 50 without departing from thescope of the present invention.

[0034] For the embodiment illustrated in FIG. 4C, a single cavity isused to form a molded section 140 for each of a plurality of chips 50.After the molded section 140 is formed, the molded section 140 may beseparated in order to form a molded section 140 a-e for each of thechips 50 in a process known as singulation. The singulation may beaccomplished by sawing apart the molded section 140, by breaking apartthe molded section 140, or by any other suitable means.

[0035] For the embodiment illustrated in FIG. 4D, a single cavity isused to form a molded section 150 for each of a plurality of a matricesof chips 50. Each matrix of chips 50 shares a single substrate and formsa multi-chip module. After the molded section 150 is formed, the moldedsection 150 may be separated in order to form a molded section 150 a-dfor each of the multi-chip modules by singulation. The singulation maybe accomplished by sawing apart the molded section 150, by breakingapart the molded section 150, or by any other suitable means.

[0036] Although the illustrated embodiment comprises four chips 50 ineach multi-chip module, it will be understood that each multi-chipmodule may comprise any suitable number of chips 50 without departingfrom the scope of the present invention. In addition, although theillustrated embodiment comprises four multi-chip modules for the moldedsection 150, it will be understood that each molded section 150 maycomprise any suitable number of multi-chip modules without departingfrom the scope of the present invention.

[0037] Although the present invention has been described with severalembodiments, various changes and modifications may be suggested to oneskilled in the art. It is intended that the present invention encompasssuch changes and modifications as fall within the scope of the appendedclaims.

What is claimed is:
 1. A method for providing a leadframeless packagestructure, comprising: providing a temporary carrier; coupling thetemporary carrier to a metal foil layer with a temporary adhesive layer;coupling an integrated circuit chip to the metal foil layer; andremoving the temporary adhesive layer and the temporary carrier to formthe leadframeless package structure after molding.
 2. The method ofclaim 1, the temporary carrier comprising one of aluminum, stainlesssteel, and laminate epoxy fiberglass.
 3. The method of claim 1, thetemporary adhesive layer comprising silicone.
 4. The method of claim 1,the metal foil layer comprising one of gold-plated copper andnon-gold-plated copper.
 5. The method of claim 1, coupling an integratedcircuit chip to the metal foil layer comprising coupling the chip to themetal foil layer with a permanent adhesive.
 6. The method of claim 5,the permanent adhesive comprising an epoxy resin.
 7. The method of claim1, further comprising patterning and etching the metal foil layer toform circuit patterns.
 8. The method of claim 7, further comprising:coupling each of a plurality of bond pads on the chip to the patternedmetal foil layer with one of a plurality of bonding wires; and forming amolding compound over the metal foil layer, the bonding wires and thechip.
 9. The method of claim 8, forming a molding compound comprisingforming the molding compound selectively over and around portions of thechip to expose a surface of the chip.
 10. A method for providing aleadframeless package structure, comprising: providing a temporarycarrier; forming a temporary adhesive layer adjacent to the temporarycarrier; forming a metal foil layer outwardly of the temporary adhesivelayer; patterning and etching the metal foil layer to form circuitpatterns; coupling an integrated circuit chip to the metal foil layer;coupling each of a plurality of bond pads on the chip to the patternedmetal foil layer with one of a plurality of bonding wires; forming amolding compound outwardly of the metal foil layer, the bonding wiresand the chip; and removing the temporary adhesive layer and thetemporary carrier to form the leadframeless package structure.
 11. Themethod of claim 10, the temporary carrier comprising one of aluminum,stainless steel, and laminate epoxy fiberglass.
 12. The method of claim10, the temporary adhesive layer comprising silicone.
 13. The method ofclaim 10, the metal foil layer comprising one of copper and gold-platedcopper.
 14. The method of claim 10, forming a molding compoundcomprising forming the molding compound selectively over and aroundportions of the chip to expose a surface of the chip.
 15. Aleadframeless package structure, comprising: a metal foil layeruncoupled from a temporary carrier; an integrated circuit chip coupledto the metal foil layer; a plurality of bonding wires, each bonding wirecoupling a specified area of the chip to the metal foil layer; and amolding compound formed outwardly of the metal foil layer, the bondingwires and the chip.
 16. The leadframeless package structure of claim 15,the metal foil layer uncoupled from the temporary carrier by removing atemporary adhesive layer coupled between the temporary carrier and themetal foil layer.
 17. The leadframeless package structure of claim 16,the temporary carrier comprising one of aluminum, stainless steel, andlaminate epoxy fiberglass and the temporary adhesive layer comprisingsilicone.
 18. The leadframeless package structure of claim 15, furthercomprising a permanent adhesive coupling the chip to the metal foillayer.
 19. The leadframeless package structure of claim 15, the metalfoil layer comprising one of copper and gold-plated copper.
 20. Aleadframeless package structure comprising a multi-chip module, themulti-chip module comprising: for each of a plurality of integratedcircuit chips, a metal foil layer uncoupled from a temporary carrier byremoving a temporary adhesive layer coupled between the temporarycarrier and the metal foil layer, a permanent adhesive coupling theintegrated circuit chip to the metal foil layer, and a plurality ofbonding wires, each bonding wire coupling a specified area of the chipto the metal foil layer; and a molding compound formed outwardly of themetal foil layers, the bonding wires and the chips.